Some integrated circuit chips have clock signal generation circuits on the chip (sometimes called a die.) The clock signal may be used for various purposes on the chip. As an example, the clock signal generation circuit may be a self-oscillating clock circuit and the clock signal may be referred to as a real time clock (RTC) signal. See, for example, Intel® ICH Family Real Time Clock (RTC) Accuracy and Considerations under Test Conditions, Application Note—AP-728, May 2006. In some chips, this clock generation circuit has had a history of problems. It can be very sensitive to silicon processing parameters as well as package and board variations.
Different approaches have been used to provide a test related to whether the clock generation circuit for a particular chip will work properly or fail. One approach is to use external testing equipment to measure the duty cycle of the RTC signal and use the duty cycle as an indicator as to whether the chip will fail. However, this approach has the following disadvantages. First, expensive external equipment is needed. In some cases, this equipment may be used anyway for other purposes, but not in all cases. Second, the RTC signal may get distorted within the chip and may lead to a different result by the time it gets to the external tester than it would within the chip. Third, changing designs may miss routing this signal outside the chip. Fourth, adjustments to the test interface unit (TIU) board adjustments may need to be done.
Another approach is to measure other characteristics than duty cycle. For example, in a currently used test suite, there is some observability of functionality of the RTC clock signal generation circuit but relatively little functionality to assess its performance and particularly its marginality. The test suite focuses on characteristics other than duty cycle, such as leakage. However, leakage might not be a good indicator as to whether the clock signal generation circuit will fail. Other characteristics may be too conservative and not a good test of whether the clock signal generation circuit will fail.
Yet another approach is to provide an on-die oscilloscope. This has the following disadvantages. First, the on-die oscilloscopes can take a relatively large amount of chip area. Second, although the accuracy of a good oscilloscope may be a benefit, the output still needs to be digitized for decision making.
Finally, phase locked loop (PLL) characterization circuits have been used. Again, although these characterizations may be useful for some purposes, they do not give the same information as the duty cycle measurements.